DIN IEC/TS 62132-9:2015-08

Techniques for generating near-fields over integrated circuits and their surrounding environment can identify the areas susceptible to radiation which could cause errors in the device. The ability to associate magnetic or electric field strengths with a particular location on a device can provide valuable information for improvement of an IC both in terms of functionality and EMC performance. Near-field scan techniques have considerably evolved over recent years. The improved efficiency, bandwidth and spatial resolution of the probes offer analysis of integrated circuits operating into the gigahertz range. Post-processing can considerably enhance the resolution of a near-field scan test bench and the measured data can be shown in various ways per user’s choice. This part of IEC 62132 provides a test procedure, which defines a method for evaluating the effect of near electric, magnetic or electromagnetic field components on an integrated circuit (IC). This diagnostic procedure is intended for IC architectural analysis such as floor planning and power distribution optimization. This test procedure is applicable to testing an IC mounted on any circuit board that is accessible to the scanning probe. In some cases it is useful to scan not only the IC but also its environment. For comparison of surface scan immunity between different ICs, the standardized test board defined in IEC 62132-1 should be used. This measurement method provides a mapping of the sensitivity (immunity) to electric- or magnetic-near-field disturbance over the IC. The resolution of the test is determined by the capability of the test probe and the precision of the Probe-positioning system. This method is intended for use up to 6 GHz. Extending the upper limit of frequency is possible with existing probe technology but is beyond the scope of this specification. The tests described in this document are carried out in the frequency domain using continuous wave (CW), amplitude modulated (AM) or pulse modulated (PM) signals. The responsible committee is DKE/K 631 "Halbleiterbauelemente" ("Semiconductor devices") of the DKE (German Commission for Electrical, Electronic and Information Technologies) at DIN and VDE.