Mechanical standardization of semiconductor devices - Part 6-20: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of small outline J-lead packages (SOJ) (Endorsed by AENOR in February of 2011.)
Publication date
2011-02-01
Original language
English
Pages
11
Publication date
2011-02-01
Original language
English
Pages
11
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